An increasingly critical limitation on computer systems is the rate at which data is transferred between a microprocessor and its associated random access memory (RAM), often referred to as the "memory bandwidth" of the system. While in the past, standard, asynchronous dynamic RAMs (DRAMs) were fast enough to provide enough bandwidth for most applications, presently, the clock speeds of microprocessors far outpaces the access times of conventional DRAMs. The need for increased memory bandwidth has led to a variety of approaches to memory designs. Fast "cache" RAMs are used in conjunction with the microprocessor to increase certain memory accesses. The high speed of cache memories requires the use of static RAMs (SRAMs). While suitable for cache applications, SRAMs are too expensive to make up the bulk of a system RAM. Where feasible, particularly for the storage of video display data, multi-port DRAMs (sometimes referred to as VRAMs for video RAMs) are used. Multi-port DRAMs are complex devices, and so, like SRAMs, are too costly to implement as basic system RAM.
Another approach to increasing memory bandwidth is the use of burst synchronous DRAMs. Burst synchronous DRAMs are timed according to a system clock and include a "burst mode" wherein multiple, synchronous, memory accesses are provided in response to a single burst memory address. A burst synchronous RAM is disclosed in U.S. Pat. No. 5,268,865 entitled SYNCHRONOUS BURST-ACCESS MEMORY and issued to Atsushi Takasugi on Dec. 7, 1993. In the burst RAM of Takasugi, a counting means counts clock pulses and generates a series of column addresses. The column addresses are coupled to a column decoding means which selects one column at a time. Decoded data are transferred via a data transfer means to an internal data bus having as many data (local I/O) lines as there are bit lines per column. The data are then provided via (global) I/O lines. A drawback to Takasugi is that if precharging is used to increase access speed, such a precharge step must occur between each cycle of the burst sequence on both the local and the global I/O lines.
Another synchronous DRAM is disclosed in U.S. Pat. No. 5,390,149 entitled SYSTEM INCLUDING A DATA PROCESSOR, A SYNCHRONOUS DRAM, A PERIPHERAL DEVICE, AND A SYSTEM CLOCK, issued to Vogley et al. on Feb. 14, 1995. Vogley et al. teaches a synchronous DRAM having an input multiplexer (MUX) and an output MUX controlled by a burst count. In a read operation, multiple blocks of data are read into an output register. The output register is coupled to an output selector gate which outputs sequential bits of the output register according to the synchronous, burst sequence. Similarly, in a write operation, data are sequentially input through an input selector gate and latched in an input register. The data are then transferred by blocks to the array. A drawback to the Vogley et al. synchronous burst DRAM is the large size of the buses used to transfer data from the array to the input and output MUXs. Such buses, often referred to as "global" input/output (I/O) lines can consume large amounts of die area. Further, every even cycle is more time consuming than the second, and subsequent cycles, as the sense amplifiers must drive the large global I/O lines to latch data in the input or output MUXs.
A drawback of all burst synchronous DRAMs is that they require a synchronous system design. Because most current computer RAM architectures are designed for asynchronous DRAMs, burst synchronous DRAMs remain incompatible with many existing computer systems. To make such systems compatible with synchronous DRAMs would typically require, at a minimum, a new DRAM controller, introducing additional cost to the system.
An alternative to burst synchronous DRAMs is the use of burst asynchronous DRAMs (referred to herein simply as "burst DRAMs"). Burst DRAMs are more easily implemented in present computer systems as they are compatible with the majority of current system RAM architectures. Burst DRAMs can provide rapid access times, particularly when combined with such options as "extended data-out" (EDO). Commonly, a burst operation in a burst DRAMs involves an initial address being accessed by a row and column address, using conventional row address strobe (RAS) and column address strobe (CAS) timing. Subsequent accesses of the burst sequence are initiated by subsequent application(s) of the CAS signal(s).
It is known in the prior art to provide a burst DRAM with an array divided into a number of subarrays, each having a number of local I/O lines. In order to ensure proper sequential operation, data on the local I/O lines are latched by local I/O latches situated proximate their respective subarrays. A drawback of this approach is that the use of such latches can consume valuable die space, increasing the overall size of the device. In addition, prior art burst DRAMs suffer from the same drawbacks as synchronous DRAMs, requiring a precharge operation between burst cycles or large amounts of die area for global I/O lines.
It would be desirable to provide a burst DRAM that eliminates the above mentioned drawbacks of the prior art.